The invention relates to a method to create topography in deposited layers.
Chemical-mechanical planarization (CMP) is frequently used to polish and planarize deposited and/or patterned surfaces during fabrication of an integrated circuit. In general, topography formed in surfaces during fabrication is undesirable. Photolithography is most accurate when depth of field is minimized; thus in general it's best to minimize topography to improve uniformity of patterned features formed on the surface. There are occasions during fabrication of an integrated circuit, however, when some topography may be advantageous, most often when this topography is outside of an array area. For example, transferred topography may be used to locate alignment and overlay marks buried beneath deposited layers. As will be described, in other instances, the presence of some topography may actually improve uniformity.
It is advantageous in some circumstances, therefore, to create topography in deposited layers in an integrated circuit.